PORTFOLIO / 2025

Aiden
Stickney

Graduate computer engineer working at the intersection of digital IC design, computer architecture, and ML‑accelerated performance modeling.

Available for work:

June 2026

CURRENTLY

Graduate Computer Engineering Student

@ Texas A&M University — Computer Engineering & Systems Group (ECEN Dept.)

Jun 2025 — May 2026

FOCUS

Digital DesignComputer ArchitecturePerformance ModelingFPGA AccelerationVerification (UVM/SVA)

Education

M.S. in Computer Engineering

Jun 2025 — May 2026

Texas A&M University

College Station, TX

GPA: 4.00

Graduate Research Assistant

B.S. in Computer Engineering

Aug 2021 — May 2025

Texas A&M University

College Station, TX

GPA: 4.00

Summa Cum LaudeUniversity Research ScholarCraig & Galen Brown Engineering Honors

Work

2023 — 2025

2025

Digital IC Design Engineering Intern

Texas Instruments (Dallas, TX)

Digital verification across coverage, formal, and CDC; authored SystemVerilog/UVM testcases, hit coverage targets, and partnered with designers to close CDC findings.

SystemVerilogUVMSVAJasperGoldVManager

2024

Research Assistant

Texas A&M University — CESG

Early‑stage performance & power prediction for OoO CPU modeling: up to 96% simulation‑time reduction (≈25×) with 2–3% IPC error; end‑to‑end pipeline from data capture to train/infer.

ChampSimPythonscikit‑learnC++

2024

Applications Engineering Intern

Texas Instruments (Dallas, TX)

Delivered a customer‑ready development board for an automotive ABS ASIC: concept → schematic/PCB (Altium), design reviews, global release. Wrote RTOS/C firmware and a web GUI; supported international trainings.

AltiumC/RTOSWeb

2023

Software Development Intern

Tyler Technologies (Plano, TX)

Contributed to product development within an Agile team.

C#TypeScriptSQL

Featured Projects

Canny Edge Detector Accelerator

Streaming Canny accelerator in Verilog with ~98% pixel‑level match to SW reference; synthesized with Synopsys DC and met timing via pipelining/resource sharing.

VerilogSynopsys DC

HTAX UVM Testbench

UVM environment (driver/monitors/scoreboard) with SVA; 100% functional & assertion coverage; 98.96% code coverage with >95% across block/expr/toggle/FSM.

SystemVerilogUVMSVAXceliumvManager

Multiclass Prediction Cache Replacement Policy

Implemented Mockingjay policy in ZSim with PC‑indexed reuse prediction and per‑line ETR; up to +43% IPC and −30% cycles vs. no‑bypass on SPEC/PARSEC.

C++ZSim

xv6 OS Multithreading Implementation

Added kernel threads (clone API), per‑thread trapframe/trampoline, and scheduler integration; ensured correct shared‑address‑space semantics.

COS

Skills

LANGUAGES

VerilogSystemVerilogSVATCLSystemCCPythonC++CUDALaTeXTypeScriptC#SQL

TECHNOLOGIES

Cadence JasperGoldVManagerVirtuosoSynopsys DCChampSimLinuxGitAltium

Certifications

Cadence Digital IC Design Fundamentals

May 2025

Cadence Jasper App for Early Design Verification

May 2025

Cadence SystemVerilog Design & Verification

Nov 2024

Coursework

COMPLETED

Advanced Digital System Design (ECEN 719)
Introduction to the design, modeling and verification of complex digital systems using hardware description language and electronic system level language.
Intro to Hardware Design Verification (CSCE 616)
Introduction to hardware functional verification; case studies on verification in integrated circuit design; introduction to industry best practices; introduction to logic functional verification.
Advanced Computer Architecture (CSCE 614)
Reviews of von Neumann architecture and its limitations; parallel computer structures and concurrent computation; pipeline computers and vectorization methods; array processors, multiprocessor architectures and programming; dataflow computers.
Intro to VLSI Design Automation (ECEN 687)
Algorithms and techniques for VLSI design automation, including basic optimization techniques, high level synthesis, logic synthesis/verification, physical design, timing verification and optimization.
Operating Systems (CSCE 410)
Hardware/software evolution leading to contemporary operating systems; basic operating systems concepts; methods of operating systems design and construction including algorithms for CPU scheduling, memory and general resource allocation, process coordination and management; case studies of several operating systems.
Microprocessor System Design (ECEN 449)
Introduction to microprocessors; 16/32 bit single board computer hardware and software designs; chip select equations for memory board design, serial and parallel I/O interfacing; ROM, static and dynamic RAM circuits for no wait-state design; assembly language programming, stack models, subroutines and I/O processing.
Digital Integrated Circuit Design (ECEN 454)
Analysis and design of digital devices and integrated circuits using MOS and bipolar technologies and computer aided simulation.

IN PROGRESS

Introduction to VLSI Systems Design (ECEN 475)
Introduction to design and fabrication of microelectronic circuits; emphasis on very large scale integration (VLSI) digital systems; use of state-of-the art design methodologies and tools; design of small to medium scale integrated circuits for fabrication.
FPGA Information Processing Systems (ECEN 722)
Signal processing and neural network implementations on field programmable gate arrays (FPGA); FPGA designs of digital filters, Fourier transform, JPEG decoding, fast convolution, Kalman filter and Viterbi decoding; circuit design techniques commonly used in signal processing and neural network, such as pipelining, parallel processing, folding, unfolding and systolic array.
Security of Embedded Systems (ECEN 426)
Security principles; common security features and flaws in day-to-day embedded systems; security analysis, vulnerability exploits and security fixes for embedded systems.

Let's Connect

stickneyaiden@gmail.com stickneyaiden@tamu.edu Personal Website GitHub LinkedIn